Semiconductor devices including sealing regions and decoupling capacitor regions

A semiconductor device comprising:

• an internal circuit on a semiconductor substrate;
• a sealing region on the semiconductor substrate, the sealing region surrounding the internal circuit;
• and
• a decoupling capacitor region comprising a plurality of decoupling capacitor layers stacked on a portion of the semiconductor substrate in the sealing region,
• wherein the plurality of decoupling capacitor layers comprise a plurality of capacitor metal wiring patterns that are spaced apart from one another and a plurality of dielectric patterns between the plurality of capacitor metal wiring patterns.

A semiconductor device comprising:

• an internal circuit on a semiconductor substrate;
• a sealing region surrounding the internal circuit and comprising:
• a plurality of metal wiring layers on the semiconductor substrate;
• and
• a plurality of metal vias that are in first inter-metal insulation layers between the plurality of metal wiring layers and interconnect the plurality of metal wiring layers;
• and
• a decoupling capacitor region in the sealing region and comprising:
• a plurality of capacitor metal wiring layers on the semiconductor substrate;
• dielectric patterns between capacitor metal wiring patterns comprising the plurality of capacitor metal wiring layers;
• and
• capacitor metal vias that are in second inter-metal insulation layers between the plurality of capacitor metal wiring layers and interconnect the plurality of capacitor metal wiring layers.