Self-Aligned Multiple Spacer Patterning Process

A method of patterning a semiconductor device, the method comprising:

• forming a plurality of hard mask layers over a semiconductor device layer;
• forming a mandrel layer over the plurality of hard mask layers;
• patterning the mandrel layer to form a first set of mandrels;
• after forming the first set of mandrels, performing a first spacer patterning process, comprising
• forming a first set of spacers on sidewalls of the first set of mandrels, the first set of spacers comprising a first material;
• and
• selectively removing the first set of mandrels without attacking the first set of spacers and the plurality of hard mask layers;
• using the first set of spacer as a second set of mandrels, performing a second spacer patterning process, comprising
• forming a second set of spacers on sidewalls of the second set of mandrels, the second set of spacers having substantially flat top surfaces and comprising a second material, the second material having an etch selectivity different from that of the first material;
• and
• selectively removing the second set of mandrels without attacking the second set of spacers and the plurality of hard mask layers;
• and
• after performing the second spacer patterning process, alternately performing the first spacer pattering process and the second spacer patterning process, wherein the first spacer patterning process uses spacers from a previous second spacer pattering process as a first set of mandrels, and wherein the second spacer patterning process uses spacers from a previous first spacer patterning process as a second set of mandrels.

A method of patterning a semiconductor device, the method comprising:

• forming one or more hard mask layers over a semiconductor device layer;
• patterning a mandrel layer over the one or more hard mask layers to form a first mandrel;
• after forming the first mandrel, iteratively performing a spacer pattering process, wherein each iteration of the spacer pattering process further comprises a first spacer patterning process followed by a second spacer patterning process, wherein the first spacer patterning process comprises
• conformally depositing a first spacer layer comprising a first material over the first mandrel and the one or more hard mask layers;
• performing a first plasma etch process to form a first set of spacers on sidewalls of the first mandrel;
• and
• selectively removing the first mandrel without attacking the first set of spacers and the one or more hard mask layers;
• and
• wherein the second spacer pattering process comprises
• using one of the first set of spacers formed in the first spacer pattering process as a second mandrel;
• conformally depositing a second spacer layer comprising a second material over the second mandrel and the one or more hard mask layers, the second material having an etch selectivity different from that of the first material;
• performing a second spacer plasma etch process to form a second set of spacers on sidewalls of the second mandrel, the second spacer plasma etch process producing substantially flat top surfaces for the second set of spacers;
• selectively removing the second mandrel without attacking the second set of spacers and the one or more hard mask layer;
• and
• using one of the second set of spacers as the first mandrel for the first spacer pattering process in a next iteration.