Screening for Data Retention Loss in Ferroelectric Memories

A method of testing a plurality of integrated circuits formed in a single integrated circuit wafer, each of the plurality of integrated circuits including ferroelectric memory cells, the method comprising the steps of:

• programming a plurality of the ferroelectric memory cells in each of the plurality of integrated circuits to a first data state;
• baking the wafer at a first elevated temperature for a first selected duration;
• then heating the wafer to a second elevated temperature lower than the first elevated temperature;
• and
• then performing a multiprobe test on the wafer at the second elevated temperature, for each of the plurality of integrated circuits, the multiprobe test comprising:
• programming the plurality of ferroelectric memory cells to the first data state;
• then programming ferroelectric memory cells in the integrated circuit to a second data state;
• then pausing for a second selected duration;
• then reading each of a plurality of sample groups of the programmed ferroelectric memory cells at a respective one of a plurality of reference voltages, to determine a number of failed cells at each of the plurality of reference voltages;
• then programming the plurality of ferroelectric memory cells to the first data state;
• then programming the plurality of ferroelectric memory cells to the second data state;
• and
• then reading each of the plurality of ferroelectric memory cells, programmed with the second data state, at a test reference voltage calculated from the numbers of failed cells at the plurality of reference voltages.

A method of testing an integrated circuit including a plurality of memory cells, comprising the steps of:

• writing the plurality of the ferroelectric memory cells to a selected data state;
• then applying a stress condition to the integrated circuit;
• then reading each of a plurality of sample groups of the memory cells at a respective one of a plurality of parameter values, to determine a number of failed cells at each of the plurality of parameter values;
• calculating a test parameter value from the numbers of failed cells at the plurality of parameter values;
• and
• then testing each of the plurality of memory cells at the test parameter value.