Circuits and methods for limiting current in random access memory cells

A memory cell array, comprising:

• a first low dropout regulator (LDO) comprising a first operational amplifier and a first PMOS transistor arranged in a closed loop, a first input of the first operational amplifier receiving a reference voltage VREF, an output of the first operational amplifier being coupled to a gate of the first PMOS transistor, and a drain of the first PMOS transistor being coupled to a second input of the first operational amplifier, the first operational amplifier outputting gate voltage Vg to the gate of the first PMOS transistor based upon a value of reference voltage VREF, the first LDO outputting bit line voltage VBL;
• a current limiter comprising a second PMOS transistor, a source of the second PMOS transistor being coupled to an input voltage VIN, a gate of the second PMOS transistor receiving a limit voltage Vplim, a drain of the second PMOS transistor being coupled to the first LDO;
• a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a resistive random access memory (RRAM) cell coupled to the first LDO, the RRAM cell comprising a first select transistor and a programmable resistor, a gate of the first select transistor being coupled to a word line and receiving a word line voltage VWL, the RRAM cell receiving as input the bit line voltage VBL from the first LDO, the programmable resistor being configured to change between a relatively high resistance and a relatively low resistance responsive to changes in a cell current ICELL through the RRAM cell based upon values of VBL and VWL;
• and
• a reference cell coupled to the gate of the second PMOS transistor of each of the memory cells, the reference cell comprising:
• a second LDO comprising a second operational amplifier and a third PMOS transistor arranged in a closed loop, a first input of the second operational amplifier receiving the reference voltage VREF, an output of the second operational amplifier being coupled to a gate of the third PMOS transistor, and a drain of the third PMOS transistor being coupled to a second input of the second operational amplifier, the second operational amplifier outputting reference gate voltage Vg,REF to the gate of the third PMOS transistor based upon a value of reference voltage VREF, the second LDO outputting reference bit line voltage VBL,REF;
• a dummy cell coupled to the second LDO, the dummy cell comprising a second select transistor and a resistor having a fixed resistance, a gate of the second select transistor being coupled to the word line and receiving the word line voltage VWL, the dummy cell receiving as input the reference bit line voltage VBL,REF from the second LDO, a current IREF through the dummy cell being based upon the fixed resistance and on the values of VBL,REF and VWL;
• and
• a mirror current limiter comprising a fourth PMOS transistor, a source of the fourth PMOS transistor being coupled to the input voltage VIN, a gate of the fourth PMOS transistor being coupled to the gate of the second PMOS transistor, a drain of the fourth PMOS transistor being coupled to the second LDO,
• wherein the value of Vplim for each memory cell is based upon a difference between the resistance of the programmable resistor of that memory cell and the fixed resistance.

A method, comprising:

• outputting a bit line voltage VBL with a low dropout regulator (LDO);
• at a resistive random access memory (RRAM) cell coupled to the LDO, receiving as input the bit line voltage VBL from the LDO;
• at a gate of a select transistor of the RRAM cell, receiving as input a word line voltage VWL;
• at a programmable resistor of the RRAM cell, changing between a relatively high resistance and a relatively low resistance responsive to changes in a cell current ICELL through the RRAM cell based upon values of VBL and VWL;
• and
• limiting current through the RRAM cell with a current limiter comprising a PMOS transistor, a gate of the PMOS transistor receiving a limit voltage Vplim, a drain of the PMOS transistor being coupled to the LDO.