Clock Switching in Always-On Component

An integrated circuit comprising:

• one or more processors;
• a memory controller and a memory;
• and
• a first circuit coupled to the one or more processors and the memory controller, wherein the first circuit is configured to:
• remain powered up during times that the one or more processors are powered down;
• receive a first plurality of audio samples captured by one or more audio input devices during a time that the one or more processors are powered down, wherein the first circuit operates according to a first clock during the time that the one or more processors are powered down;
• detect a predetermined pattern in the first plurality of audio samples;
• cause the memory controller to power up and initialize the memory controller to store the first plurality of audio samples in a memory responsive to detecting the predetermined pattern;
• cause the one or more processors to power up responsive to detecting the predetermined pattern, wherein a second clock activates responsive to the power up;
• and
• switch to the second clock responsive to the second clock becoming operable at a time that is not near an arrival of a subsequent second plurality of audio samples.

A system comprising:

• an audio input device;
• an audio coder/decoder (codec) coupled to the audio input device and configured to generate audio samples from sound detected by the audio input device;
• a memory;
• and
• an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes an audio filter circuit, one or more processors, and a memory controller coupled to the memory, and wherein:
• the audio filter circuit is configured to detect a predetermined pattern in the audio samples from the audio codec during a time that a memory controller and the one or more processors are powered down, wherein the audio filter circuit operates according to a first clock during the time;
• the audio filter circuit is configured to cause the memory controller and the processors to power up responsive to detecting the predetermined pattern, wherein the power up causes a second clock to activate in the integrated circuit;
• and
• the audio filter circuit configured to switch from the first clock to the second clock responsive to activation of the second clock at a time that is not near an arrival of subsequent audio samples.