Programming memory controllers to allow performance of active memory operations
AssigneeHewlett Packard Enterprise Development LP
InventorsKevin T. Lim, Naveen Muralimanohar
Life of this patent
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Abstract
Example implementations relate to performing active memory operations. In example implementations, a memory controller may be programmed such that the memory controller allocates more time for a standard memory operation than required by a timing specification of a memory communicatively coupled to the memory controller. Extra time that is allocated for the standard memory operation may be identified. An active memory operation may be performed during the extra time.
Claims15
A method for performing active memory operations, the method comprising:
- causing a memory controller to be programmed such that the memory controller allocates more time for a standard memory operation than required by a timing specification of a first memory, wherein the memory controller is communicatively coupled to the first memory;
- identifying extra time allocated for the standard memory operation;
- and
- performing an active memory operation during the extra time.
A system for performing active memory operations, the system comprising:
- a volatile memory, wherein data stored in the volatile memory is periodically refreshed;
- and
- an active memory communicatively coupled to the volatile memory and to a first memory controller, wherein the active memory is to:
- cause a register of the first memory controller to be programmed such that the first memory controller allocates more time for refreshing the volatile memory than required by a timing specification of the volatile memory;
- identify extra time allocated for refreshing the volatile memory;
- and
- perform an active memory operation during the extra time.
A system for performing active memory operations, the system comprising:
- a volatile memory;
- an active memory communicatively coupled to the volatile memory and to a first memory controller, wherein the active memory is to:
- cause a register of the first memory controller to be programmed such that the first memory controller allocates time, for a standard memory operation, based on operation of the volatile memory at a first frequency;
- cause, during the allocated time, the standard memory operation to be performed on the volatile memory, wherein the volatile memory is operated at a second frequency higher than the first frequency during the allocated time;
- and
- perform an active memory operation during the allocated time.
Dependencies are inferred from the claim text.