Enhanced status monitor for scan testing
AssigneeFreescale Semiconductor, Inc.
InventorsLing Wang, HUANGSHENG DING, WEI ZHANG
Life of this patent
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Abstract
An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.
Claims20
An integrated circuit (IC), comprising:
- core logic;
- scan test hardware integrated with the core logic for performing scan testing on the core logic based on a scan clock and a scan data input signal to generate a scan data output signal, wherein the scan clock is phase encoded with test-control information;
- and
- an enhanced status monitor that receives the scan clock and a test clock, wherein the enhanced status monitor (i) decodes the phase-encoded scan clock relative to the test clock to recover the test-control information and (ii) uses the test-control information to selectively store enhanced test status data.
A method for enhanced test status monitoring within an integrated circuit (IC), comprising:
- decoding phase-encoded test-control information from a scan clock and a test clock, the scan clock otherwise dedicated to scan-test hardware associated with core logic within the IC;
- and
- using the test-control information to direct selectively storing enhanced test status data used in the enhanced test status monitoring.
Dependencies are inferred from the claim text.