Differential Odd Integer Divider
AssigneeTexas Instruments Incorporated
InventorSudipto Chakraborty
Life of this patent
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Abstract
A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.
Claims17
An apparatus for performing odd-integer division in a radio or high frequency clocking systems receiver, the apparatus comprising:
- a set of delay cells connected in a ring with an output of one delay cell electrically connected to an input of a next delay cell in the ring;
- wherein individual ones of the delay cells comprise:
- a dual port output having a first output port and a second output port;
- a first switch and a second switch having source terminals connected to a power voltage or a ground voltage;
- wherein the first switch's gate is electrically connected to a first electrical node connected to the second switch's drain and the second output port,
- wherein the second switch's gate is electrically connected to a second electrical node connected to the first switch's drain and the first output port;
- dual port differential inputs comprising:
- a first positive input port connected to a gate of a first input positive switch transistor having a first input positive switch transistor drain electrically connected to the second electrical node;
- a first negative input port connected to a gate of a first input negative switch transistor having a first input negative switch transistor drain electrically connected to the first electrical node;
- a second positive input port connected to a gate of a second input positive switch transistor having a second input positive switch transistor source electrically connected to the ground voltage or the power voltage, and a second input positive switch transistor drain connected to a first input positive switch transistor source;
- a second negative input port connected to a gate of a second input negative switch transistor having an input switch source electrically connected to the ground voltage or the power voltage, and the drain connected to a second input negative switch transistor source.
A method of performing odd-integer division in radio or high frequency clocking systems receiver, the method comprising:
- receiving an input signal at a first delay cell of a set of delay cells connected in a ring with an output of one delay cell electrically connected to an input of a next delay cell in the ring;
- outputting from an Nth delay cell of the set of delay cells (M) an output signal comprising an Nth phasor of the input signal divided by M.
An apparatus for performing odd-integer division in radio or high frequency clocking systems receiver, the apparatus comprising:
- a set of delay cells connected in a ring with an output of one delay cell is electrically connected to an input of a next delay cell in the ring;
- a controller configured to bypass individual ones of the set of delay cells to effect a division of an input signal by a different divider based on a number of delay cells of the set of delay cells not bypassed;
- wherein individual ones of the delay cells comprise:
- a dual port output having a first output port and a second output port;
- a first switch and a second switch having sources connected to a power voltage;
- wherein the first switch's gate is electrically connected to a first electrical node connected to the second switch's drain and the second output port,
- wherein the second switch's gate is electrically connected to a second electrical node connected to the first switch's drain and the first output port;
- a dual port input comprising:
- a first input port connected to a gate of a first input switch having an input switch source electrically connected to the first electrical node,
- a second input port connected to a gate of a second input switch having an input switch source electrically connected to the second electrical node;
- a dual port clock signal input comprising:
- a first clock signal input port connected to a gate of a first clock signal input switch having:
- a clock signal input switch source electrically connected to a drain of the first input switch, and
- a clock signal input switch drain electrically connected to ground for the apparatus;
- a second clock signal input port connected to a gate of a second clock signal input switch having:
- a clock signal input switch source electrically connected to a drain of the second input switch, and
- a clock signal input switch drain electrically connected to ground for the apparatus.
- wherein:
- the first switch and the second switch having sources connected to the power voltage both comprise either NMOS or PMOS transistors,
- the first input switch and the second input switch both comprise either NMOS or PMOS transistors but not a same type as the first switch and the second switch having sources connected to the power voltage, and
- the first clock signal switch and the second clock signal switch both comprise either NMOS or PMOS transistors but not a same type as the first switch and the second switch having sources connected to the power voltage.
Dependencies are inferred from the claim text.