US 2016/0072508 A1 · SHARED DIVIDE BY N CLOCK DIVIDER

Abstract

A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.

Claims16

Dependent claims

A method of providing multiple clock frequencies for an integrated circuit (IC) including a plurality of modules, comprising:

frequency division processing of at least one reference clock signal (fin) to generate sub-divider outputs of said fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals each providing a frequency divider factor (divider factor) in a predetermined divider range including at least one divider factor that is not equal to 2N, and
for at least a portion of others of said divider factors that are not said prime numbers or said prime numbers raised to an integer power, combining combinations of two or more of said sub-divider outputs to generate additional clock signals that each provide an additional divider factor;
a first of said plurality of modules frequency selecting at least a first selected clock signal from said plurality of prime number-based clock signals and said additional clock signals, and a second of said plurality of modules-frequency selecting at least a second selected clock signal from said plurality of prime number-based clock signals and said additional clock signals.

A microcontroller unit (MCU) chip, comprising:

a substrate having a plurality of modules, a digital data bus, an address bus, a divide by N clock divider (clock divider), and frequency selector circuits formed therein and thereon, said plurality of modules including:
at least one analog-to-digital converter (ADC);
a pulse-width modulation (PWM) driver;
a non-volatile (NV) program memory;
a digital I/O (interface);
a central processing unit (CPU), and
said clock divider including:
a sub-divider block including a plurality of frequency sub-dividers (sub-dividers) for frequency division processing at least one received reference clock signal (fin) and for generating sub-divider outputs of said fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals each providing a frequency divider factor (divider factor) in a predetermined divider range including at least one divider factor that is not equal to 2N, and
a frequency combination circuit block including frequency combination circuits coupled to receive said sub-divider outputs for generating at least a portion of others of said divider factors that are not said prime numbers or said prime numbers raised to an integer power for combining combinations of two or more of said sub-divider outputs to generate additional clock signals that each provide an additional divider factor;
said digital data bus and said address bus for coupling together said ADC, said NV program memory, said digital I/O (interface), said CPU, and said clock divider, and
said frequency selector circuits for two or more of said plurality of modules coupled to receive said plurality of prime number-based clock signals and said additional clock signals for performing frequency selecting and selecting one or more of said plurality of prime number-based clock signals and said additional clock signals to output at least one custom clock frequency.

8 more elements

Dependencies are inferred from the claim text.

Shared divide by n clock divider

Life of this patent

Shared divide by n clock divider

Life of this patent

Abstract

Claims16