Low power divide-by-seven divider

A method of operating a divide-by-seven divider, comprising:

• storing a count between 0 and 3 in a count cycle within a first module, the first module being clocked with a clock input;
• clocking a second module with an output of the first module, the second module being coupled to the first module;
• causing, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle, the feedback module being coupled between the first module and the second module, the first module, the second module, and the feedback module being configured to divide the clock input by seven;
• and
• outputting the divided clock input.

A divide-by-seven divider apparatus, comprising:

• means for storing a count between 0 and 3 in a count cycle within a first module, the first module being clocked with a clock input;
• means for clocking a second module with an output of the first module, the second module being coupled to the first module;
• means for causing, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle, the feedback module being coupled between the first module and the second module, the first module, the second module, and the feedback module being configured to divide the clock input by seven;
• and
• means for outputting the divided clock input.