Counter
AssigneeNuvoton Technology Corporation
InventorTsung-Hsien Hsieh
Life of this patent
Estimating the term…
Abstract
A counter including a state determination unit and a counter reset unit is provided. The state determination unit is for receiving a current count value to calculate a next count value. The counter reset unit compares a reset counter value and a delay cycle value to determine using a first comparator or a second comparator, and compares the reset counter value and the current count value to output a counter reset signal to the state determination unit to reset the current count value, wherein a bit number of the first comparator is smaller than a bit number of the second comparator.
Claims14
A counter, configured to output a count value having N bits, wherein N is a positive integer, the counter comprising:
- a state determination unit, receiving a current count value to calculate a next count value of the counter, wherein the count value has a high bit count part and a low bit count part;
- a value analyzing unit, receiving and outputting a reset counter value, comparing the reset counter value and a delay cycle value to output a value comparing signal;
- and
- a count comparing unit, receiving a clock signal, determining to use a first comparator or a second comparator based on the value comparing signal, and outputting a reset counter signal to the state determination unit to reset the count value based on a comparison result and the clock signal, wherein a bit number of the first comparator is smaller than a bit number of the second comparator.
A counter, configured to output a count value having N bits, wherein N is a positive integer, the counter comprising:
- a state determination unit, receiving a current count value to calculate a next count value of the counter, wherein the count value has a high bit count part and a low bit count part, the state determination unit comprising:
- a count enabling unit, receiving the current count value to output a plurality of count enabling signals respectively corresponding to the N bits of the count value, wherein the count enabling signals are enabled when levels of the corresponding bits change;
- and
- a value counting unit, receiving the count enabling signals to determine and provide the next count value of the counter;
- and
- a reset counter unit, receiving a reset counter value and the current count value and comparing the reset counter value and the current count value to output a reset counter signal to the state determination unit to reset the count value.
Dependencies are inferred from the claim text.