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AssigneeFreescale Semiconductor, Inc.
InventorsNishant Singh Thakur, Rakesh Pandey, Manmohan Rana
Estimating the term…
Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
An apparatus for preventing multiple resets in an integrated circuit device, the apparatus comprising:
An integrated circuit including an apparatus for preventing multiple resets in said integrated circuit, the apparatus comprising:
A method for preventing multiple resets in an integrated circuit device, wherein the integrated circuit device includes a power controller, the method comprising:
Dependencies are inferred from the claim text.