Vertical floating gate nand with offset dual control gates
AssigneeSanDisk Technologies LLC
InventorsJames Kai, Vinod Purayath, Donovan Lee, Akira Matsudaira
Life of this patent
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Abstract
A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.
Claims22
A method of making a monolithic three dimensional NAND string, comprising:
- providing a stack of alternating insulating layers and control gate films over a major surface of a substrate, each of the control gate films comprising:
- a middle layer located between a first control gate layer and a second control gate layer, the middle layer comprising a different material from the first and second control gate layers and from the insulating layers;
- forming a front side opening in the stack;
- and
- forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.
A monolithic three dimensional NAND string, comprising:
- a stack of alternating insulating layers and control gate films over a major surface of a substrate, each of the control gate films comprising:
- an insulating middle layer located between a first control gate layer and a second control gate layer, the insulating middle layer comprising a different material from the first and second control gate layers and from the insulating layers;
- a semiconductor channel, wherein at least one end of the semiconductor channel extends through the stack substantially perpendicular to the major surface of the substrate;
- a first charge storage region and a first portion of a blocking dielectric located in a recess between the first and the second control gate layers of a first control gate film in a first device level, wherein the first portion of the blocking dielectric is located between the first charge storage region and the insulating middle layer of the first control gate film;
- a first electrically conductive connection layer which contacts the first and second control gate layers in the first control gate film, wherein the first electrically conductive connection layer is separated from the first charge storage region by the insulating middle layer of the first control gate film;
- a second charge storage region and a second portion of the blocking dielectric located in a recess between the first and the second control gate layers of a second control gate film in a second device level, wherein the second portion of the blocking dielectric is located between the second charge storage region and the insulating middle layer of the second control gate film;
- a second electrically conductive connection layer which contacts the first and second control gate layers in the second control gate film, wherein the second electrically conductive connection layer is separated from the second charge storage region by the insulating middle layer of the second control gate film;
- and
- a tunnel dielectric located between the semiconductor channel and the first and second charge storage regions.
Dependencies are inferred from the claim text.