Vertical transistor static random access memory cell
AssigneeGlobalfoundries Inc.
InventorsKwan-Yong Lim, Ryan Ryoung-Han Kim
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Abstract
Various methods of forming a vertical static random access memory cell and the resulting devices are disclosed. One method includes forming a plurality of pillars of semiconductor material on a substrate, forming first source/drain regions on a lower portion of each of the pillars, forming a gate electrode around each of the pillars above the first source/drain region, forming a second source/drain region on a top portion of each of the pillars above the gate electrode, wherein the first and second source/drain regions and the gate electrode on each pillar defines a vertical transistor, and interconnecting the vertical transistors to define a static random access memory cell.
Claims20
A method, comprising:
- forming a plurality of pillars of semiconductor material on a substrate;
- forming first source/drain regions on a lower portion of each of said pillars;
- forming a gate electrode around each of said pillars above said first source/drain region;
- forming a second source/drain region on a top portion of each of said pillars above said gate electrode, wherein said first and second source/drain regions and said gate electrode on each of said pillars defines a vertical transistor;
- and
- interconnecting said vertical transistors to define a static random access memory cell.
A memory cell, comprising:
- a plurality of vertical transistors, each comprising:
- a pillar of semiconductor material;
- a first source/drain region on a lower portion of said pillar;
- a gate electrode disposed around said pillar above said first source/drain region;
- a second source/drain region on a top portion of said pillar above said gate electrode;
- and
- interconnections between said vertical transistors to define a static random access memory cell.
A memory array, comprising:
- a plurality of devices arranged in columns and rows, each device comprising:
- a plurality of vertical transistors, each comprising:
- a pillar of semiconductor material;
- a first source/drain region on a lower portion of said pillar;
- a gate electrode disposed around said pillar above said first source/drain region;
- a second source/drain region on a top portion of said pillar above said gate electrode;
- and
- interconnections between said vertical transistors to define a static random access memory cell including first and second pass gate transistors, first and second pull-down transistors, and first and second pull-up transistors;
- a plurality of bit line pairs, each pair coupled to said second source/drain regions of respective first and second pass gates of a column of devices;
- and
- a plurality of word lines, each coupled to said gate electrodes of said first and second pass gates of a row of static random access memory cells.
Dependencies are inferred from the claim text.