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US 2015/0318226 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsBo-Na BAEK, Seok-Won LEE, Eun-Seok CHO, Dong-Han KIM, Kyoung-Sei CHOI, Sa-Yoon KANG
Life of this patent
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Abstract
Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.
Claims20
A semiconductor package, comprising:
- a semiconductor chip;
- an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient;
- and
- a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.
1 more element
A semiconductor package, comprising:
- a semiconductor chip;
- a die attach film on an upper surface of the semiconductor chip;
- a reinforcing plate attached to the die attach film;
- an upper insulating layer on the reinforcing plate;
- a lower insulating layer under the semiconductor chip;
- and
- a conductive pattern in the lower insulating layer and electrically connected to the semiconductor chip,
- an average of thermal expansion coefficients of the die attach film and the upper insulating layer being greater than or equal to a thermal expansion coefficient of the lower insulating layer, and the reinforcing plate having a thickness greater than a thickness of the conductive pattern.
5 more elements
A semiconductor package, comprising:
- a semiconductor chip;
- an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient and including:
- an upper insulating layer on an upper surface of the semiconductor chip, and
- an upper plug through the upper insulating layer;
- and
- a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient, a difference between the first thermal expansion coefficient and the second thermal expansion coefficient being greater than or equal to about 30 ppm.
3 more elements
Dependencies are inferred from the claim text.