Memory array test logic

A method, comprising:

• providing at least one signal to enable a first subset of a plurality of word lines in a first stage of a plurality of stages in a ring oscillator to produce a first oscillation frequency, the plurality of stages comprising a plurality of bit cells to store information;
• providing the at least one enable signal to a second subset of the plurality of word lines to produce a second oscillation frequency;
• and
• determining a read current for the bit cells based on the first and second oscillation frequencies.

A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate a computer system to perform a portion of a process to fabricate at least part of a processor, the processor comprising:

• a plurality of stages coupled in a ring, each stage comprising:
• a plurality of bit cells to store information;
• a bit line and a complementary bit line coupled to the plurality of bit cells;
• and
• a plurality of word lines coupled to the plurality of bit cells, wherein subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on at least one of the bit line and the complementary bit line of another one of the plurality of stages;
• and
• inversion logic deployed between two of the plurality of stages.