Test structure of display panel and test structure of tested display panel

A test structure of a tested display panel, the display panel having a display region, a non-display region, and a buffer display region between the display region and the non-display region, the test structure being located within the buffer display region of the display panel and comprising:

• a substrate;
• at least one signal line disposed on the substrate;
• an insulation layer covering the at least one signal line;
• a planar layer disposed on the insulation layer, the planar layer having at least one opening exposing a portion of the insulation layer;
• and
• an electrode layer disposed on the planar layer, the electrode layer having a display electrode portion, at least one test electrode portion, at least one ring-shaped trench, and a conductive channel, wherein the at least one ring-shaped trench surrounds the at least one test electrode portion and exposes a portion of the planar layer, the at least one test electrode portion is connected to the insulation layer via the at least one opening of the planar layer, the conductive channel extends from the at least one test electrode portion to the at least one signal line, the at least one test electrode portion is electrically connected to the at least one signal line through the conductive channel, and the display electrode portion is located on the planar layer, surrounds the at least one ring-shaped trench, and is electrically insulated from the at least one test electrode portion.