Implementation of load acquire/store release instructions using load/store operation with dmb operation

A method for executing instructions in a processor, comprising:

• executing a load with acquire instruction for performing memory operation ordering, wherein the executing the load with acquire instruction comprises executing a load operation followed by a data memory barrier operation.

A processor that executes computer-executable instructions to perform operations, the instructions comprising:

• a store with release instruction that performs memory operation ordering, wherein the store with release instruction comprise a first data memory barrier operation followed by a store operation followed by a second data memory barrier operation.

A method for executing instructions in a processor, comprising:

• executing a store with release instruction for performing memory operation ordering, wherein executing the store with release instruction comprises executing a first data memory barrier operation followed by executing a store operation followed by executing a second data memory barrier operation.