Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code

A computing device, comprising:

• one or more processors configured to:
• receive information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
• determine information associated with a permutation matrix for the LDPC code,
• the permutation matrix including a group of rows,
• each row, of the group of rows, corresponding to a check node element of a group of check node elements associated with the LDPC code,
• the permutation matrix including a group of columns,
• each column, of the group of columns, corresponding to a variable node element of a group of variable node elements associated with the LDPC code, and
• the permutation matrix including a set of values,
• each value, of the set of values, corresponding to a particular check node element, of the group of check node elements, and a particular variable node element of the group of variable node elements, and
• each value, of the set of values, identifying a connection between the particular check node element and the particular variable node element;
• compute a parallelization factor associated with the permutation matrix,
• the parallelization factor being computed based on the set of values included in the permutation matrix;
• determine, based on the parallelization factor, whether the permutation matrix satisfies the design threshold;
• and
• provide information indicating whether the permutation matrix satisfies the design threshold.

A method, comprising:

• determining, by a device, information that identifies a design threshold associated with a low-density parity-check (LDPC) code;
• receiving, by the device, information associated with a permutation matrix associated with designing the LDPC code,
• the permutation matrix including a group of rows,
• each row, of the group of rows, corresponding to a processing element of a group of processing elements associated with the LDPC code,
• the permutation matrix including a group of columns,
• each column, of the group of columns, corresponding to a storage element of a group of storage elements associated with the LDPC code, and
• the permutation matrix including a set of values,
• each value, of the set of values, corresponding to a particular processing element, of the group of processing elements, and a particular storage element of the group of storage elements, and
• each value, of the set of values, identifying a connection between the particular processing element and the particular storage element;
• determining, by the device, a parallelization factor associated with the permutation matrix,
• the parallelization factor being computed based on the set of values included in the permutation matrix;
• identifying, by the device and based on the parallelization factor, whether the permutation matrix satisfies the design threshold;
• and
• providing, by the device, information indicating whether the permutation matrix satisfies the design threshold.