Distributed virtual-ground switching for sar and pipelined adc

A system that comprises:

• a capacitor array, each capacitor of the capacitor array having a top plate and having a bottom plate configured to drive an output signal;
• a plurality of switch groups, each switch group corresponding to a respective capacitor of the capacitor array, and including:
• a first switch configured to provide an input signal;
• a second switch configured to provide a first reference voltage signal;
• and
• a third switch configured to provide a second reference voltage signal;
• and
• a signal buffer array, each signal buffer of the signal buffer array corresponding to a respective capacitor of the capacitor array and to a respective switch group of the plurality of switch groups, each signal buffer including:
• an output terminal communicatively coupled to the top plate of the corresponding respective capacitor;
• and
• a first input terminal communicatively coupled to each switch of the corresponding respective switch group.

A method, comprising:

• receiving during a first phase of a control signal, by a plurality of signal buffers, an input data signal through a plurality of switches, each signal buffer of the plurality of signal buffers receiving the input data signal from a respective switch of the plurality of switches;
• receiving during the first phase of the control signal, by a top plate of each of a plurality of capacitors, a buffered data signal generated from the input data signal by a corresponding signal buffer of the plurality of signal buffers, the bottom plate of each of the plurality of capacitors being coupled to a first reference voltage;
• decoupling the bottom plates from the first reference voltage during the first phase of the control signal subsequent to receiving the buffered data signal;
• receiving during a second phase of the control signal, by the top plate of each of the plurality of capacitors, a buffered data signal generated from one of a second or a third reference voltage by a corresponding signal buffer of the plurality of signal buffers;
• comparing, by a comparator, a plurality of output signals from bottom plates of the plurality of capacitors to a fourth reference voltage to generate a first digital output bit during the second phase of the control signal;
• selecting one of the second and third references voltages to apply to an input of a first signal buffer of the plurality of signal buffers based on the generated first digital output bit;
• generating during the second phase of the control signal, by the first signal buffer, a corresponding first buffered data signal based on the selected one of the second and third reference voltages, the first buffered data signal received by the top plate of a corresponding capacitor of the plurality of capacitors;
• and
• comparing, by the comparator, the plurality of output signals from the bottom plates of the plurality of capacitors to the fourth reference voltage to generate a second digital output bit during the second phase of the control signal.