Memory cells having a common gate terminal
AssigneeMicron Technology, Inc.
InventorsRajesh N. Gupta, Farid Nemati
Life of this patent
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Abstract
Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
Claims21
-20. (canceled)
A method of forming an array of memory cells, the method comprising:
- forming a first metal material on a substrate;
- forming a material stack on a portion of the first metal material;
- removing a portion of the material stack to form a common gate region;
- forming a first isolation material on a portion of the first metal material;
- forming a gate dielectric material on a portion of the material stack;
- forming a common gate conductive material in a portion of the common gate region;
- forming a dielectric material on the common gate conductive material;
- and
- forming a second metal material on a portion of the material stack.
A method of forming an array of memory cells, the method comprising:
- forming a first doped semiconductor material on a portion of a first metal material;
- forming a material stack on a portion of the first doped semiconductor material, wherein the material stack includes a first isolation material, a common gate conductive material, and a second isolation material;
- removing a portion of the material stack;
- forming a gate dielectric material on a portion of the common gate conductive material;
- forming a base semiconductor material on a portion of the gate dielectric material;
- forming a second doped semiconductor material on a portion of the base semiconductor material;
- and
- forming a resistive storage element on a portion of the second doped semiconductor material.
A method of forming an array of memory cells, the method comprising:
- forming a first group of memory cells, each including a resistive storage element coupled to a select device, wherein the group includes at least three memory cells such that at least two of the three memory cells are physically connected to a first sense line and at least two of the three memory cells are physically connected to a first access line;
- wherein each select device includes a base semiconductor material, a first terminal, a second terminal, and a first group gate terminal;
- and
- wherein the first group gate terminal of each select device is common to each memory cell of the group.
Dependencies are inferred from the claim text.