Thin film transistor array panel

A thin film transistor array panel comprising:

• a gate line disposed on a substrate and including a gate electrode;
• a gate insulating layer disposed on the gate line;
• a semiconductor layer including an oxide semiconductor disposed on the gate insulating layer, wherein the semiconductor layer extends in a longitudinal direction and includes a projection which extends toward the gate electrode;
• and
• a data line intersecting the gate line;
• a source electrode connected to the data line;
• a drain electrode facing the source electrode, and
• a passivation layer disposed on the data line, the drain electrode and on a portion of the projection of the semiconductor layer disposed between the source electrode and the drain electrode,
• wherein the data line, the source electrode and the drain electrode each include a barrier layer, a main wiring layer disposed on the barrier layer, and a capping layer disposed on the main wiring layer,
• wherein the main wiring layer includes a metal or a metal alloy,
• wherein the barrier layer and the capping layer includes a metal oxide, and
• wherein the capping layer is in a polycrystalline state.