Three-dimensional semiconductor memory device

A three-dimensional (3D) semiconductor memory device, comprising:

• a lower structure including a lower gate pattern and a lower semiconductor pattern penetrating the lower gate pattern, the lower semiconductor pattern being connected to a substrate;
• and
• an upper structure including upper gate patterns stacked on the lower structure, an upper semiconductor pattern penetrating the upper gate patterns, and a vertical insulator between the upper semiconductor pattern and the upper gate patterns, the upper semiconductor pattern being connected to the lower semiconductor pattern,
• wherein the lower semiconductor pattern has a rounded sidewall adjacent to the lower gate pattern.

A three-dimensional (3D) semiconductor memory device, comprising:

• a stack structure including insulating layers vertically stacked on a substrate and a lower gate pattern between the insulating layers;
• and
• a lower semiconductor pattern penetrating the lower gate pattern and being connected to the substrate, the lower semiconductor pattern including first portions adjacent to the insulating layers and a second portion adjacent to the lower gate pattern,
• wherein the second portion of the lower gate pattern has a rounded sidewall.