Structure and Method for FinFET Device

A fin-like field-effect transistor (FinFET) device comprising:

• a substrate having an n-type fin-like field-effect transistor (NFET) region;
• wherein the NFET region includes:
• a first gate stack wrapping over an upper portion of a first fin structure, wherein the first fin structure has an epitaxial silicon (Si) layer as its upper portion, an epitaxial silicon germanium (SiGe) with a silicon germanium oxide (SiGeO) feature at its outer layer as its middle portion and an epitaxial Si as its bottom portion;
• a first source/drain (S/D) feature over a recessed upper portion of the first fin structure;
• and
• a second S/D feature over a second fin structure over the substrate, wherein the second fin structure has a recessed epitaxial Si layer as its upper portion, a dielectric layer with a liner wrapping on its top and bottom surface, as its middle portion and the epitaxial Si as its bottom portion;
• and
• wherein two adjacent first gate stacks is separated by either the S/D feature over the first fin structure or the S/D feature over the second fin structure.

A method, comprising:

• providing a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;
• forming first fin structures in the NFET region and the PFEN region, the first fin structure includes:
• a first epitaxial semiconductor material layer as its upper portion;
• a second epitaxial semiconductor material layer, with a semiconductor oxide feature at its outer layer, as its middle portion;
• and
• a third semiconductor material layer as its bottom portion;
• forming a first patterned hard-mask (HM) over the NFET region and PFEN region;
• forming a lateral trench;
• forming a second pattern HM over the NFET region and PFEN region to expose the second semiconductor material layer in the lateral trench in the NFET region;
• applying annealing to form a semiconductor oxide feature at out layer of the exposed second semiconductor material layer to form a second fin structure;
• forming a liner wrapping over the first and the second fin structures in both of the NFET region and the PFET region;
• depositing a dielectric layer to form a dielectric anchor in the lateral trench to form a third fin structure;
• forming a fourth and a fifth fin structures in the PFET region while covering the NFET region with a third HM;
• recessing the dielectric layer in both of the NFET region and the PFET region to expose upper portions of the first, second, third, fourth and fifth fin structures, and depositing a dummy dielectric layer over the exposed first, second, third, fourth and fifth fin structures.