US 2015/0310154 A1 · METHOD AND APPARATUS FOR TESTING

Abstract

A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.

Claims20

Dependent claims

A computer-implemented method performed by a computerized device, comprising:

receiving a design;
receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design;
translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine;
activating the engine and providing the input to the engine, whereby the engine outputting a result;
and
displaying the result.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/259,163Filed 23 Apr 2014

Published

29 Oct 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 30/3308
Design verification, e.g. functional simulation or model checking: using simulation
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3323
Design verification, e.g. functional simulation or model checking: using formal methods, e.g. equivalence checking or property checking

Method and apparatus for testing

Life of this patent

Method and apparatus for testing

Life of this patent

Abstract

Claims20