Data bus driving circuit, and semiconductor device and semiconductor memory device including the same

A semiconductor memory device comprising:

• a memory cell array;
• an ECC decoding unit that performs error correction processing, based on an error correction code, on data read out from the memory cell array, and outputs the corrected data;
• a first logic inversion unit that selects, based on a determination result signal, one of the corrected data and inverted data obtained by logically inverting each value of a plurality of bits constituting the corrected data, and outputs the selected data to a data bus;
• and
• an inversion determination unit that compares the data output from the first logic inversion unit with the data that has not been corrected, and outputs the determination result signal based on a comparison result.