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US 2015/0213841 A1Published application
Memory chip and memory storage device
AssigneeEorex Corporation
InventorsCHENG-LUNG LIN, WAN-TUNG LIANG, CHENG-WEI HSU
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Abstract
A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads. The plurality of memory pads are disposed around the substrate so as to form a pattern, and the plurality of memory pads are configured in a mirror horizontal manner and with layout line connectivity, so as to simplify complexity of layout line. Mirror solder ball map of the instant disclosure increases design flexibility and convenience of integrating line characteristics of the end product's application, and is easy to achieve the design of doubling the memory capacity.
Claims10
A memory, comprising:
- a substrate;
- and
- a plurality of memory pads, disposed around the substrate so as to form a pattern, configured in a mirror horizontal manner and with layout line connectivity, so as to simplify complexity of layout line, wherein the memory pads are divided into a first data region and a second data region, a first address region and a second address region, a first control region and a second control region, a first command region and a second command region, a first system voltage region and a second system voltage region, and a first ground region and a second ground region;
- wherein the first data region and the second data region are configured to be electrically connected to a processing unit so as to be a data storage medium, and the first control region and the second control region are configured to be electrically connected to the processing unit so as to receive at least one control signal and to control the processing unit for accessing data of the first data region and the second data region.
1 more element
A memory storage device, comprising:
- a processing unit;
- a first memory, electrically connected to the processing unit, having a storage space of X bits wherein X is two to the power of N and N is an integer;
- and
- a second memory, electrically connected to the first memory, wherein the second memory and the first memory are the same, and the first memory comprising:
- a substrate;
- and
- a plurality of memory pads, disposed around the substrate so as to form a pattern, and the memory pads are configured in a mirror horizontal manner and with layout line connectivity, wherein the plurality of memory pads are divided into a first data region and a second data region, a first address region and a second address region, a first control region and a second control region, a first system voltage region and a second system voltage region, and a first ground region and a second ground region;
- wherein the first data region and the second data region are configured to be electrically connected to the processing unit so as to be a data storage medium, the first control region and the second control region are configured to be electrically connected to the processing unit so as to receive at least one control signal and to control the processing unit for accessing data of the first data region and the second data region wherein the first data regions of the first memory and the second memory are configured with layout line connectivity, the second data regions of the first memory and the second memory are configured with layout line connectivity, the first address regions of the first memory and the second memory are configured with layout line connectivity, the second address regions of the first memory and the second memory are configured with layout line connectivity, the first system voltage regions of the first memory and the second memory are configured with layout line connectivity, the second system voltage regions of the first memory and the second memory are configured with layout line connectivity, the first ground regions of the first memory and the second memory are configured with layout line connectivity, and the second ground regions of the first memory and the second memory are configured with layout line connectivity so as to expand memory capacity and to simplify complexity of layout line.
5 more elements
Dependencies are inferred from the claim text.