Back to results
US 2015/0178438 A1Published application
Semiconductor manufacturing using design verification with markers
OwnerErtugrul Demircan, Douglas M. Reber +2inventors
InventorsERTUGRUL DEMIRCAN, Douglas M. Reber, Michael A. Stockinger, Edward O. Travis
Life of this patent
Estimating the term…
Abstract
A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule.
Claims20
A method comprising:
- entering a first circuit design in an electronic design automation (EDA) computer system, wherein the first circuit design includes a first feature with a first node;
- providing a marker that represents a voltage associated with the first node as an algebraic expression of a first numerical value, wherein the first numerical value represents a property of the first circuit design;
- and
- using the marker for a determination if the first feature of the first circuit design causes a design rule violation.
1 more element
A method comprising:
- receiving at least one circuit layout file, the at least one circuit layout file includes:
- a circuit design having a first feature that includes a first node, wherein the first feature is spaced from a second feature by a first distance;
- a marker associated with the first node, wherein the marker represents a voltage which is calculated with an algebraic expression using a numerical representation of a property of the circuit design;
- and
- checking design rules for the circuit design in an electronic design automation (EDA) computer system using the marker to determine if the first distance is in compliance with the design rules.
2 more elements
An apparatus comprising:
- a tangible computer storage medium including at least one circuit layout file, the at least one circuit layout file is readable by an electronic design automation (EDA) computer system and includes a circuit design having a feature with a node and a marker associated with the node, wherein the marker specifies a voltage associated with the node calculated with an algebraic expression using a numerical representation of a property of the circuit design.
Dependencies are inferred from the claim text.