US 2015/0178436 A1 · CLOCK ASSIGNMENTS FOR PROGRAMMABLE LOGIC DEVICE

Abstract

Various techniques are provided to perform clock assignments in a programmable logic device (PLD). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD), synthesizing the design into a plurality of components of the PLD configured to perform the operations, and performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD. Additional methods, systems, machine-readable mediums, and other techniques are also provided.

Claims20

Dependent claims

A computer-implemented method comprising:

receiving a design identifying operations to be performed by a programmable logic device (PLD);
synthesizing the design into a plurality of components of the PLD configured to perform the operations;
and
performing a simulated annealing process to determine a layout of the components in the PLD based on a system cost including a clock assignment cost for global clock signals of the PLD.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/136,482Filed 20 Dec 2013

Published

25 Jun 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/396
Circuit design at the physical level: clock trees

Clock assignments for programmable logic device

Life of this patent

Clock assignments for programmable logic device

Life of this patent

Abstract

Claims20