Stacked multiple-input delay gates

A computer program product for correcting early-mode timing violations in a chip design, the computer program product comprising:

• one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions comprising:
• program instructions to perform logic synthesis of a digital circuit design to create a netlist, wherein the netlist includes a portion of the digital circuit design having an early-mode timing violation;
• program instructions to identify the portion of the digital circuit design having the early-mode timing violation;
• program instructions to identify a first logic circuit within the identified portion having the early-mode timing violation;
• program instructions to identify at least one input of the logic circuit having the early-mode timing violation;
• program instructions to replace the first logic circuit with an alternative logic circuit in the digital circuit design, wherein, when compared to the first logic circuit, the alternative logic circuit includes at least one additional transistor connected in series on one or both of a PMOS side and an NMOS side of the alternative logic circuit, and wherein the alternative logic circuit is configured to utilize the least one additional transistor to delay a signal received at an input of the an alternative logic circuit to eliminate the early-mode timing violation;
• and
• program instructions to manufacture a circuit based, at least in part, on the digital circuit design.

A logic circuit corrected to eliminate an early-mode timing violation in a digital circuit design, the logic circuit comprising:

• a plurality of transistors configured to perform a logical function on a plurality of input signals to produce at least one output signal, wherein the plurality of input signals includes a first input signal and a second input signal;
• at least one input terminal of at least one first transistor of the plurality of transistors coupled to the first input signal;
• and
• a first set of at least two input terminals of at least two second transistors of the plurality of transistors coupled to the second input signal, wherein the at least two input terminals of the at least two second transistors have a greater capacitive load than the at least one input terminal of the at least one first transistor, and wherein the greater capacitive load delays a response of the second input signal on the plurality of transistors.