Satisfying memory ordering requirements between partial reads and non-snoop accesses

An apparatus comprising:

• a home agent to:
• receive a read invalidate message from a first coherency agent, wherein the read invalidate message corresponds to a particular cache line and a snoop invalidate message is to be sent to correspond with the read invalidate message;
• receive a writeback message from a second coherency agent in response to the snoop invalidate message, wherein the writeback message is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state;
• and
• perform a write to the particular cache line based on the writeback message.

An apparatus comprising:

• a cache coherency agent to:
• receive a snoop invalidate invalid to exclusive (SnpInvItoE) message, wherein the SnpInvItoE message corresponds to a partial read of a particular cache line by another cache coherency agent and is to flush any modified state data related to the particular cache line to a home agent, and the partial read is to comprise a read invalidate own (RdInvOwn) message;
• and
• generate a writeback modified to invalidate (WbMtoI) message in response to the snoop invalidate message, wherein the WbMtoI message is to indicate a writeback of invalid data (WbIData) to the home agent and is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

An apparatus comprising:

• a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple to a link comprising a plurality of lanes;
• the interface logic to:
• receive a snoop invalidate message, wherein the snoop invalidate message corresponds to a particular cache line;
• and
• send a writeback message responsive to the snoop invalidate message, wherein the writeback message is to indicate a write to a home agent associated with the particular cache line and cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.

A system comprising:

• cache coherent memory;
• a first device comprising a first coherency agent to send a read invalidate message, wherein the read invalidate message corresponds to a particular cache line of the cache coherent memory;
• a second device comprising a second coherency agent to receive a snoop invalidate message associated with the read invalidate message and generate a writeback message associated with the read invalidate message;
• and
• a third device comprising a home agent to receive the writeback message and perform a write to the particular cache line based on the writeback message, wherein the writeback message is to cause a transition of the particular cache line from a modified cache coherency state to an invalid cache coherency state.