Error Resilient Pipeline

An apparatus comprising:

• a dynamic adaptable resilient pipeline (DARP) controller that determines a minimum error pipeline stage of a processor instruction pipeline with a minimum number of errors and determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors, wherein the DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold and decreases the clock frequency if the minimum number of errors exceeds an error constant.

A system comprising:

• an instruction pipeline for a processor;
• and
• a dynamic adaptable resilient pipeline (DARP) controller that determines a minimum error pipeline stage of the instruction pipeline with a minimum number of errors and determines a maximum error pipeline stage of the instruction pipeline with a maximum number of errors, wherein the DARP controller increases a clock frequency for the instruction pipeline if the minimum number of errors of the minimum error pipeline stage is zero and the maximum number of errors of the maximum error pipeline stage does not exceed an error threshold and decreases the clock frequency if the minimum number of errors exceeds an error constant.