Multi-core fuse decompression mechanism

An apparatus for storing and decompressing configuration data in a multi-core microprocessor, the apparatus comprising:

• a shared fuse array, disposed on a die, said shared fuse array comprising a plurality of semiconductor fuses programmed with compressed configuration data, said shared fuse array comprising:
• a first plurality of fuses;
• a second plurality of fuses;
• a third plurality of fuses;
• and
• a fourth plurality of fuses;
• and
• a plurality of microprocessor cores, disposed on said die, wherein each of said plurality of microprocessor cores is coupled to said shared fuse array and is configured to access all of said compressed configuration data during power-up/reset, for initialization of elements within said each of said plurality of cores, said each of said plurality of cores comprising:
• a reset controller, configured to decompress said all of said compressed configuration data, and to distribute decompressed configuration data to initialize said elements.

A method for storing and decompressing configuration data to a multi-core microprocessor, the method comprising:

• first disposing a shared fuse array on a die, wherein the shared fuse array comprises a plurality of semiconductor fuses;
• second disposing a plurality of microprocessor cores on the die, and coupling each of the plurality of cores to the shared fuse array;
• programming the plurality of semiconductor fuses with compressed configuration data for the each of the plurality of cores;
• and
• via a reset controller within the each of the plurality of cores, accessing, decompressing, and distributing all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.