Context save and restore
AssigneeIntel Corporation
InventorsZeev Offen, Inder M. Sodhi
Life of this patent
Estimating the term…
Abstract
Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.
Claims25
A processor comprising:
- a plurality of processor cores;
- a plurality of design blocks coupled to the plurality of processor cores, each design block including a set of registers coupled to gated power, the set of registers to store active context of the design block;
- and
- logic circuitry coupled to the plurality of cores and the plurality of design blocks, to monitor access to the set of registers of each design block to detect a change in the active context, and to store an indication of one or more of the design blocks that includes the change in the active context.
A logic circuit comprising:
- logic on a processor coupled to a plurality of processor cores and a plurality of design blocks, to monitor access to a set of registers of each design block to detect a change in the set of registers that store an active context, and to store an indication that one or more design blocks of the plurality of design blocks have changes to the active context;
- and
- a power manager coupled to the logic to manage power to the plurality of cores and the plurality of design blocks.
A system comprising:
- a processor including a design blocks and a system agent, the system agent to monitor access to the design block by a core of the processor to detect a change to a set of registers storing active context of the design block, wherein responsive to detecting the change in the set of registers, the system agent sets a first status bit indicating that the active context of the design block has been changed, and the system agent further sets a bit-field corresponding to a subset of the set of registers that have changed from a reset value of the block;
- a power manager to manage a power source coupled to the design block;
- and
- a display device coupled to an external display.
A method comprising:
- monitoring access to a block of a processor to detect a change to a set of registers storing context of the block;
- responsive to detecting the change in the set of registers, setting a first status bit indicating that the context of the block has been changed, and setting a bit-field corresponding to a subset of the set of registers that have changed from a reset value of the block;
- and
- during a context save event, saving the set of registers of the block to memory when the first status bit is set and bypassing the set of registers of the block when the first status bit is not set, wherein the first status bit is reset after saving the set of registers.
Dependencies are inferred from the claim text.