Instruction and Logic for Memory Disambiguation in an Out-of-Order Processor

A method comprising, within a processor:

• receiving an instruction stream, the instruction stream previously reordered by a software scheduler and including a plurality of memory operations, each of the plurality of memory operations associated with a set of alias information, the alias information indicating how a given memory operation may be evaluated;
• reordering, in hardware, the instruction stream for out-of-order execution by resources of the processor;
• executing the instruction stream out-of-order;
• determining, for a given memory operation and based upon the set of alias information, a checking range of memory atoms subsequent to the given memory operation in the instruction stream and a virtual order of the memory operation, the virtual order indicating an original ordering of instructions before reordering by the software scheduler;
• reordering, after execution and before retirement of instructions of the instruction stream, the instruction stream according to an order as received;
• determining whether the reordering of the instruction stream in hardware and subsequent execution caused a data dependency error;
• and
• determine, based upon the checking range and the virtual order, whether the reordering of the instruction stream by the software scheduler and subsequent execution caused a data dependency error for the given memory operation when compared to the memory atoms.

A system comprising:

• an interface to receive an instruction stream as reordered by a software scheduler, each of the plurality of memory operations associated with a set of alias information;
• and
• a processor communicatively coupled to the interface and to execute the instruction stream, including:
• a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution by resources of the processor;
• a calculation module to determine, for a given memory operation and based upon the set of alias information, a check range of memory atoms subsequent to the given memory operation in the instruction stream and a virtual order of the memory operation, the virtual order to indicate an original order of the instructions;
• and
• an alias unit to:
• after execution and before retirement of instructions of the instruction stream, reorder the instruction stream based on an order as received by the front end;
• determine whether the reorder of the instruction stream in hardware and subsequent execution caused a data dependency error;
• and
• determine, based upon the check range and the virtual order, whether the reorder of the instruction stream by the software scheduler and subsequent execution caused a data dependency error for the given memory operation when compared to the memory atoms.