Instructions and logic to provide base register swap status verification functionality
OwnerH. Peter Anvin, Scott D. Rodgersinventors
Life of this patent
Estimating the term…
Loading patent…
OwnerH. Peter Anvin, Scott D. Rodgersinventors
Estimating the term…
Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.
A processor comprising:
A method comprising:
A machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine causes the machine to:
A processing system comprising:
A method comprising:
Dependencies are inferred from the claim text.