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US 2015/0178077 A1Published application
Instruction and Logic for Non-Blocking Register Reclamation
AssigneeIntel Corporation
InventorsSRIKANTH T. SRINIVASAN, MARK J. DECHENE, YURY N. ILIN, JUSTIN M. DEINLEIN, CHRISTINE E. WANG, MATTHEW C. MERTEN
Life of this patent
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Abstract
A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.
Claims20
A processor, comprising:
- a first logic to execute a first instruction and a second instruction, the first instruction ordered before the second instruction, the first instruction including a reference a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
- and
- a second logic to reassign the second physical register to another logical register before retirement of the first instruction.
A method comprising, within a processor:
- executing a first instruction and a second instruction, the first instruction ordered before the second instruction, the first instruction including a reference a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
- and
- reassigning the second physical register to another logical register before retirement of the first instruction.
A system comprising:
- an interface to receive a first instruction and a second instruction;
- a processor, including:
- a first logic to execute the first instruction and the second instruction, the first instruction ordered before the second instruction, the first instruction including a reference a first logical register assigned to a first physical register, the second instruction including a reference to a second logical register assigned to a second physical register;
- and
- a second logic to reassign the second physical register to another logical register before retirement of the first instruction.
2 more elements
Dependencies are inferred from the claim text.