Information processing device
AssigneeKabushiki Kaisha Toshiba
InventorsNobuhiro Kondo, Kenichi Maeda
Life of this patent
Estimating the term…
Abstract
According to one embodiment, an information processing device includes: a host device, a semiconductor memory device with a nonvolatile semiconductor memory, and a communication path connecting the host device and the semiconductor memory device together.
Claims17
An information processing device comprising a host device, a semiconductor memory device with a nonvolatile semiconductor memory, and a communication path connecting the host device and the semiconductor memory device,
- wherein the host device comprises:
- a first storage section;
- and
- a first control section to which the first storage section and the communication path are connected and which controls the first storage section,
- the communication path comprises:
- a plurality of ports to each of which a priority is assigned,
- the semiconductor memory device comprises:
- a second control section to which the communication path is connected to, and configured to transmits a first command containing a first flag that indicates a priority, the first flag being determined based on a type or size of a data that is transmitted or received to and from the first storage section,
- upon receiving the first command, the first control section carries out transmission and reception between the first storage section and the second control section via the port assigned a priority corresponding to the priority indicated by the first flag contained in the first command.
An information processing device comprising a host device, a semiconductor memory device with a nonvolatile semiconductor memory, and a communication path connecting the host device and the semiconductor memory device,
- wherein the host device comprises:
- a first storage section;
- and
- a first control section to which the first storage section and the communication path are connected and which controls the first storage section,
- the communication path comprises:
- a plurality of ports to each of which a priority is assigned,
- the semiconductor memory device comprises:
- a second control section to which the communication path is connected to, and configured to transmits a first command containing a first flag that indicates a priority, the first flag being determined based on a first information that is transmitted from the host device,
- upon receiving the first command, the first control section carries out transmission and reception between the first storage section and the second control section via the port corresponding to the priority based on the first flag contained in the first command.
A memory system comprising a nonvolatile semiconductor memory and being connectable to a host device via a communication path, the memory system comprising:
- a second control section to which the communication path is connected to, and configured to transmits a first command containing a first flag that indicates the priority, the first flag being determined based on a type or size of a data that is transmitted or received to and from a first storage section of the host device,
- wherein the second control section receives data indicated by the first command via a port assigned a priority corresponding to the priority indicated by the first flag contained in the first command.
Dependencies are inferred from the claim text.