Array substrate, display panel, display device and method for driving array substrate

A display panel, comprising an array substrate, wherein the array substrate comprises:

• gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode;
• and the array substrate further comprises compensation capacitors on the array substrate;
• in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs;
• and
• in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and an other end electrically connected to a gate line in a next row.

A method for driving an array substrate, wherein the array substrate comprises gate lines on the array substrate, data lines on the array substrate, pixel TFTs and pixel electrodes on the array substrate, wherein each row of pixel TFTs have gates electrically connected with a gate line, and each column of pixel TFTs have first electrodes electrically connected with a data line, and each pixel TFT has a second electrode connected with a pixel electrode;

• and the array substrate further comprises compensation capacitors on the array substrate;
• in every two adjacent rows of gate lines in at least a part of the rows on the array substrate, pixel TFTs connected with one gate line are a first type of TFTs, and pixel TFTs connected with an other gate line are a second type of TFTs;
• and in the at least a part of the rows, each of the pixel electrodes is arranged correspondingly with one of the compensation capacitors, and each of the compensation capacitors has one end electrically connected to the pixel electrode corresponding thereto and an other end electrically connected to a gate line in a next row,
• and wherein the method comprises:
• for every two adjacent rows of gate lines in the at least a part of the rows,
• outputting a first turn-on signal to a preceding gate line of the two adjacent rows of gate lines in a scanning cycle of the preceding gate line, so that pixel TFTs electrically connected with the preceding gate line can be turned on by the first turn-on signal;
• and outputting a second turn-on signal to a succeeding gate line of the two adjacent rows of gate lines in a scanning cycle of the succeeding gate line, so that pixel TFTs electrically connected with the succeeding gate line can be turned on by the second turn-on signal, wherein the scanning cycles of these two adjacent rows of gate lines overlap with each other, and the first turn-on signal is opposite in phase to the second turn-on signal.