Device for testing and monitoring digital circuits

A device for testing and monitoring digital circuits enabling the detection of timing faults affecting a signal D received directly at the input of a flip-flop called primary sampling element, said primary sampling element supplying a first value D1 of the signal D and receiving a first clock signal for its updating, said testing and monitoring device comprising at least:

• a scan logic module introducing a latency in the signal D, said scan logic module having a first input receiving the signal “D”, a second input receiving a “scan in” signal and a third input receiving a “scan enable” signal adapted for selecting the operating mode of the testing and monitoring device in a scan mode or an operational mode, and an output linked to a secondary sampling element of the signal “D” and supplying a second sampled signal D2 of the signal D after passing through the scan logic module, said secondary sampling element receiving a second clock signal (105b) for updating its state, and
• a module for comparison of the signal D1 and the signal D2 generating an alert or error signal.