Testing a processor assembly

A method for testing comprising:

• providing a testing backplane comprising
• a plurality of first test ports, the plurality first test ports configured to receive a first processor assembly, the first processor assembly comprising a target processor assembly under test, the plurality of first test ports comprising one of an even number of first test ports and an odd number of first test ports;
• a plurality of second test ports, wherein each first test port corresponds to a second test port, the plurality of second test ports connecting to a second processor assembly;
• and
• a signal pathway from each first test port to a second test port, the signal pathway comprising a signal path length, the signal path length within a range between a maximum signal path length and a minimum signal path length,
• wherein each port on the first processor assembly corresponds to each port on the second processor assembly, and
• wherein the testing backplane is configured differently from a backplane used as a final destination for operating the first processor assembly;
• connecting a first processor assembly to the plurality of first test ports;
• and
• testing the first processor assembly by communicating over the signal pathways between the plurality of first test ports and the plurality of second test ports.

A testing backplane apparatus comprising:

• a substrate;
• a plurality of first test ports on the substrate, the plurality first test ports configured to receive a first processor assembly, the first processor assembly comprising a target processor assembly under test, the plurality of first test ports comprising one of an even number of first test ports and an odd number of first test ports;
• a plurality of second test ports on the substrate, wherein each first test port corresponds to a second test port, the plurality of second test ports connecting to a second processor assembly;
• and
• a signal pathway from each first test port to a second test port, wherein each signal pathway comprises a trace on the substrate comprising a signal path length, the signal path length within a range between a maximum signal path length and a minimum signal path length,
• wherein the second processor assembly comprises one of
• a second target processor assembly under test;
• a target processor assembly previously tested and found to be functioning;
• and
• processor assembly components built onto the substrate,
• wherein each port on the first processor assembly corresponds to each port on the second processor assembly, and
• wherein the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.