Back to results
US 2015/0149795 A1Published application
Semiconductor Device and Electronic Device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKazunori Watanabe
Life of this patent
Estimating the term…
Abstract
To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled.
Claims22
(canceled)
A semiconductor device comprising:
- a power source circuit comprising:
- a voltage converter circuit configured to generate a potential by using a first clock signal, the voltage converter circuit comprising a first transistor;
- and
- a CPU core comprising:
- a register comprising:
- a first memory circuit configured to store data, the first memory circuit being supplied with a second clock signal;
- and
- a second memory circuit configured to store the data output from the first memory circuit, the second memory circuit comprising a second transistor and a first capacitor,
- wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
- wherein a back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,
- wherein one of a source and a drain of the second transistor is electrically connected to the first capacitor, and
- wherein a back gate of the second transistor is capable of being supplied with the potential.
9 more elements
A semiconductor device comprising:
- a power source circuit comprising:
- a first voltage converter circuit configured to generate a first potential by using a first clock signal, the first voltage converter circuit comprising a first transistor;
- and
- a second voltage converter circuit configured to generate a second potential by using a second clock signal, the second voltage converter circuit comprising a second transistor;
- and
- a CPU core comprising:
- a register comprising:
- a first memory circuit configured to store data, the first memory circuit being supplied with a third clock signal;
- and
- a second memory circuit configured to store the data output from the first memory circuit, the second memory circuit comprising a third transistor and a first capacitor,
- wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
- wherein a back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,
- wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein a back gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to the first capacitor, and
- wherein a back gate of the second transistor is capable of being supplied with the first potential or the second potential.
13 more elements
A semiconductor device comprising:
- a power source circuit comprising:
- a first voltage converter circuit configured to generate a first potential, the first voltage converter circuit comprising a first transistor;
- and
- a second voltage converter circuit configured to generate a second potential, the second voltage converter circuit comprising a second transistor;
- an oscillator configured to output a clock signal to the power source circuit;
- and
- a CPU core configured to control whether an operation of the oscillator is stopped or not, the CPU core comprising:
- a register comprising:
- a first memory circuit configured to store data in a period during which a power source voltage is applied to the CPU core;
- and
- a second memory circuit configured to store data in a period during which supply of the power source voltage to the CPU core is stopped, the second memory circuit comprising a third transistor and a first capacitor,
- wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
- wherein a back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,
- wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein a back gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to the first capacitor, and
- wherein the CPU core is further configured to control whether the first potential or the second potential is applied to a back gate of the third transistor.
14 more elements
Dependencies are inferred from the claim text.