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US 2015/0149672 A1Published application
Clockless virtual gpio
AssigneeQUALCOMM Incorporated
InventorsLalan Jee Mishra, Richard Dominic Wietfeldt, Mohit Kishore Prasad
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Abstract
A virtual GPIO architecture for an integrated circuit is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.
Claims23
An integrated circuit, comprising:
- a plurality of GPIO pins:
- a GPIO interface configured to receive a first set of signals from a processor and to provide a GPIO portion of the first set of signals to the plurality of GPIO pins for transmission to a remote processor as GPIO signals;
- a dedicated transmit pin;
- and
- a finite state machine (FSM) configured to receive a virtual GPIO portion of the first set of signals from the GPIO interface as a transmit set of virtual GPIO signals and to serially transmit the transmit set of virtual GPIO signals as a series of corresponding pulse-width-modulated signals to a remote processor over the dedicated transmit pin.
2 more elements
A method, comprising:
- at a GPIO interface for a processor within an integrated circuit, receiving a first set of signals from the processor;
- pulse-width-modulating the first set of signals from the GPIO interface into a corresponding first series of pulse-width-modulated signals;
- and
- serially transmitting the first series of pulse-width-modulated signals through a dedicated transmit pin for the integrated circuit to a remote processor.
1 more element
An integrated circuit, comprising:
- a plurality of GPIO pins:
- a GPIO interface configured to receive a first set of signals from a processor within the integrated circuit and to provide a GPIO portion of the first set of signals to the GPIO pins for transmission to a remote processor as GPIO signals;
- a dedicated transmit pin;
- and
- an oscillator;
- means for serially processing each signal in a remaining portion of the first set of signals from the GPIO interface into a series of corresponding pulse-width-modulated signals, wherein the means is configured to determine a pulse width for each serially processed signal by counting oscillations from the oscillator into one of a first count and a second count responsive to a binary value of the serially processed signal, and wherein the means is further configured to transmit the series of corresponding pulse-width-modulated signals through the dedicated transmit pin to a remote processor over the dedicated transmit pin.
3 more elements
Dependencies are inferred from the claim text.