Fast normalization in a mixed precision floating-point unit
AssigneeInternational Business Machines Corporation
InventorsMaarten J. Boersma, Thomas Fuchs, Markus Kaltenbach, David Lang
Life of this patent
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Abstract
A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.
Claims9
A method for returning scalar single precision denormal results to double precision normal results in architected format, the method comprising:
- counting leading zeros of an unrounded single precision denormal result;
- pre-computing a first exponent and a second exponent for the unrounded single precision denormal result;
- and
- performing a second normalization of the rounded single precision denormal result back to architected format.
Dependencies are inferred from the claim text.