Reader receivers and reader transceivers including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJun-Ho Kim, Il-Jong Song, Hang-Seok Choi
Life of this patent
Estimating the term…
Abstract
Reader receivers including a sample clock providing unit are provided. The sample clock providing unit may be configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal.
Claims20
A reader receiver, comprising:
- a sample clock providing circuit configured to generate a plurality of delayed clock signals by controlling a phase of an initial clock signal, configured to select one of the plurality of delayed clock signals as a sample clock signal based on an input signal and further configured to provide an I phase sample clock signal and a Q phase sample clock signal based on the sample clock signal;
- a mixer configured to convert the input signal into base band signals in synchronization with the I phase sample clock signal and the Q phase sample clock signal, respectively;
- and
- a base band signal processing circuit configured to filter and amplify the base band signals.
A reader transceiver comprising:
- a reader transmitter configured to transmit an output signal in synchronization with a transmission clock signal;
- and
- a reader receiver configured to process an input signal, wherein the reader receiver includes:
- a sample clock providing circuit configured to generate a plurality of delayed clock signals by controlling a phase of an initial clock signal, configured to select one of the plurality of delayed clock signals as a sample clock signal based on an input signal and further configured to provide an I phase sample clock signal and a Q phase sample clock signal based on the sample clock signal;
- a mixer configured to convert the input signal into base band signals in synchronization with the I phase sample clock signal and the Q phase sample clock signal, respectively;
- and
- a base band signal processing circuit configured to filter and amplify the base band signals.
A near field communication (NFC) receiver, comprising:
- a sample clock generator configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal recovered from an input signal;
- and
- a mixer configured to convert the input signal into a pair of base band signals that are synchronized with the first and second sample clock signals.
Dependencies are inferred from the claim text.