Methods and apparatus to reduce signaling power

An apparatus, comprising:

• means for determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;
• means for generating transmission symbols from the plurality of input data symbols, wherein primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction;
• and
• means for providing the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.

An apparatus, comprising:

• one or more multi-state encoders configured to encode transmission symbols as multi-level transmission symbols for transmission on a pulse amplitude modulated communications link;
• a processing circuit configured to:
• determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;
• generate the transmission symbols from the plurality of input data symbols, wherein primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction;
• and
• provide the transmission symbols to the one or more multi-state encoders.

A processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:

• determine a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;
• generate transmission symbols from the plurality of input data symbols, wherein primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction;
• and
• provide the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.

A method, comprising:

• decoding a multi-level encoding indicator signal received from a communications link to provide a plurality of control signals;
• selectively inverting a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals;
• selectively inverting a secondary bit of the data symbols based on a second of the plurality of control signals;
• and
• selectively swapping the primary bit and the secondary bit based on a third of the plurality of control signals,
• wherein more power is required to transmit a primary bit or a secondary bit in a first logic state than in a second logic state.

An apparatus, comprising:

• a multi-state decoder configured to decode a multi-level encoding indicator signal received from a communications link and to provide a plurality of control signals extracted from the encoding indicator signal;
• and
• a processing circuit configured to:
• selectively invert a primary bit of data symbols decoded from one or more signals received from the communications link based on a first of the plurality of control signals;
• selectively invert a secondary bit of the data symbols based on a second of the plurality of control signals;
• and
• selectively swap the primary bit and the secondary bit based on a third of the plurality of control signals,
• wherein more power is required to transmit a primary bit or secondary bit in a first logic state than in a second logic state.