US 2015/0146495 A1 · SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT

Abstract

Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Claims20

Dependent claims

An apparatus comprising:

a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals;
and
a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Dependencies are inferred from the claim text.

Facts

Application

14/555,131Filed 26 Nov 2014

Priority

JP 2013-24622528 Nov 2013

Published

28 May 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 8/18
Arrangements for selecting an address in a digital store: address timing or clocking circuits; Address control signal generation or management,…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters

Semiconductor device including a clock adjustment circuit

Life of this patent

Semiconductor device including a clock adjustment circuit

Life of this patent

Abstract

Claims20