Semiconductor devices
AssigneeSK hynix Inc.
InventorYong Suk JOO
Life of this patent
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Abstract
The semiconductor device includes an input clock generator and a data input unit. The input clock generator generates an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal. The data input unit receives data and generates first input data in response to the first pulse of the input clock signal and receives the data and generates second input data in response of the second pulse of the input clock signal.
Claims20
A semiconductor device comprising:
- an input clock generator suitable for generating an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal;
- and
- a data input unit suitable for receiving data and generating first input data in response to the first pulse of the input clock signal and suitable for receiving the data and generating second input data in response to the second pulse of the input clock signal.
A semiconductor device comprising:
- a burst signal generator suitable for generating a first burst signal including a pulse generated in response to a write signal and a write latency signal during a write operation and suitable for generating a second burst signal including a pulse generated in response to an external command signal and a burst length signal;
- and
- an input clock output unit suitable for generating an input clock signal, wherein the input clock signal is enabled when the first and second burst signals are generated.
A system comprising:
- a memory controller;
- and
- a semiconductor memory device comprising:
- an input clock generator suitable for generating an input clock signal including a first pulse and a second pulse, wherein the first pulse is generated in response to a write signal and a write latency signal and the second pulse is generated in response to an external command signal and a burst length signal;
- and
- a data input unit suitable for receiving data and generating first input data in response to the first pulse of the input clock signal and suitable for receiving the data and generating second input data in response to the second pulse of the input clock signal.
Dependencies are inferred from the claim text.