In-memory computational device
AssigneeGsi Technology Israel Ltd.
InventorsAvidan AKERIB, Eli EHRMAN
Life of this patent
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Abstract
A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each column of the memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0. The computing device additionally includes at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from the first section and a decoder to activate a word line connected to a cell in the column in the second section to write the bit line voltage into the cell.
Claims20
A computing device comprising:
- a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0;
- and
- at least one multiplexer to connect a bit line in a column of a first section to a bit line in a column in a second section different from said first section;
- and
- a decoder to activate a word line connected to a cell in said column in said second section to write said bit line voltage into said cell.
A method of performing in-memory computations in a memory array comprising a plurality of sections having memory cells arranged in rows and column, at least one cell in each column of said memory array connected to a bit line having a bit line voltage associated with a logical 1 or a logical 0, the method comprising:
- connecting a bit line in a column of a first section to a bit line in a column in a second section different from said first section;
- and
- activating a word line connected to a cell in said column in said second section;
- and
- writing said bit line voltage into said cell.
Dependencies are inferred from the claim text.