Non-volatile memory with reduced sub-threshold leakage during program and erase operations

A method, comprising:

• configuring a non-volatile memory cell, including an NMOS select transistor and a floating gate transistor connected to the NMOS select transistor in series between a bit line and a source line, in a programming mode;
• and
• driving a gate terminal of the NMOS select transistor with a negative bias voltage in response to said memory cell being configured in programming mode to program a data value into said floating gate transistor, said negative bias voltage producing a negative gate-to-source voltage on said NMOS select transistor.

A method, comprising:

• configuring a non-volatile memory cell including an NMOS select transistor and a floating gate transistor series connected to the NMOS select transistor in an erase mode;
• and
• driving a gate terminal of an NMOS pull-down transistor coupled to said memory cell with a negative bias voltage in response to said memory cell being configured in erase mode to erase a data value stored on said floating gate transistor.